The present invention relates to multi-dimensional integrated circuits. More specifically it relates to design conversion from a field programmable device (FPGA) to different density metal programmable application specific devices (MPGA) to reduce cost and improve performance, power and reliability.
Traditionally, integrated circuit (IC) devices such as custom, semi-custom, or application specific integrated circuit (ASIC) devices have been used in electronic products to reduce cost, enhance performance or meet space constraints. However, the design and fabrication of custom or semi-custom ICs can be time consuming and expensive. The customization involves a lengthy design cycle during the product definition phase and high Non Recurring Engineering (NRE) costs during manufacturing phase. When device geometries shrink, signal timing in an ASIC is wire-delay dominant. Wire delays are non-predictable during synthesis & placement phase, and comprise “RC” extractions of post-placement result of the best guess placement. Thus timing closure becomes a significant bottle neck in ASIC designs. Further, should errors exist in the custom or semi-custom ICs, the design/fabrication cycle has to be repeated, further aggravating the time to market and engineering cost. As a result, ASICs serve only specific applications and are custom built for high volume and low cost applications.
Another type of semi custom devices called Gate Array, Structured Array, Structured ASIC or Metal Programmable Gate Arrays (MPGA), henceforth all termed MPGAs, customizes modular blocks at a reduced NRE cost by synthesizing the design using a software model similar to the ASIC. The logic arrays are pre-fabricated; while only one or more metal layers are customize to fit the design with lower utilization over ASICs. The missing apriori wire-delays make the MPGA timing closure as difficult as in the ASIC. The missing silicon level design verification results in multiple spins and lengthy design iterations.
In recent years there has been a move away from custom or semi-custom ICs towards field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. Off the shelf, generic Programmable Logic Device (PLD) or Field Programmable Gate Array (FPGA) products, henceforth all termed FPGAs, greatly simplify the design cycle. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to optimize silicon performance. All wire delays are pre-characterized and FPGAs offer easy timing closure in a predictable manner thus solving ASIC and MPGA biggest problem. The flexibility of this programmability is expensive in terms of silicon real estate, but reduces design cycle and upfront NRE cost to the designer.
FPGAs offer the advantages of low non-recurring engineering costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes to a few hours), and low risk since designs can be easily amended late on in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the more traditional approaches. However, the conversion from an FPGA implementation to an MPGA or ASIC implementation typically requires a complete redesign. Such redesign is undesirable in that the FPGA design effort is wasted.
Compared to an FPGA, an ASIC or MPGA has hard-wired logic connections, identified during the chip design phase, and need no configuration memory cells. They further require much less wires to connect logic. This is a large chip area and cost saving for the ASIC. Smaller ASIC die sizes lead to better performance. A full custom ASIC also has customized logic functions which take less gate counts compared to PLD and FPGA configurations of the same functions. Thus, an ASIC is significantly smaller, faster, cheaper and more reliable than an equivalent gate-count FPGA. The trade-off is between time-to-market (PLD and FPGA advantage) versus low cost and better reliability (ASIC pr MPGA advantage).
There is no convenient timing exact migration path from an FPGA used as a design verification and prototyping vehicle to the lower die size (hence lower cost) ASIC or MPGA. All of the SRAM or Anti-fuse configuration bits and programming circuitry that makes the FPGA more expensive has no value to the ASIC or MPGA. Programmable module removal from the FPGA and the ensuing layout and design customization is time consuming with severe timing variations from the original design. Input/output pad position changes also impact signal timing.
There is no convenient timing improvement or power reduction path from an FPGA used as a design verification and prototyping vehicle to the lower die size ASIC or MPGA. All of the SRAM or Anti-fuse configuration bits and programming circuitry that makes wire delays slow and power consumption high has no value to the ASIC or MPGA. Programmable module removal from the FPGA and the ensuing layout and design customization is time consuming with severe non-predictable timing variations from the original design.
There is no convenient single prototype FPGA that can be used as a design verification and prototyping vehicle, and provide an easy bit-stream compatible design conversion to a lower cost, or better performance, or lower power, or smaller density ASIC or MPGA. All of the configuration and programming overhead & pre-connected parasitic overhead within the FPGA has no value to the ASIC or MPGA. Parasitic overhead removal from the FPGA and the ensuing layout and design customization is time consuming with severe non-predictable timing variations from the original design.
What is therefore needed is a single prototype FPGA that can be used as design verification and prototyping vehicle, and further provide easy bit-stream compatible design conversion to more user desirable one or more MPGA products comprising varying densities for production.